1. Field of the Invention
The invention relates generally to output buffers and more particularly to output buffers incorporating a pull-up transistor and a pull-down transistor.
2. Description of the Related Art
The use of an output buffer circuit which employs a pull-up transistor and a pull-down transistor is well known. In particular, the use of a CMOS output buffer circuit which includes a p-channel pull-up transistor and an n-channel pull-down transistor is well known. During low to high output signal transitions, the p-channel transistor pulls up the voltage provided at an output terminal while the n-channel transistor is cutoff. During high to low transitions, the n-channel transistor pulls down the voltage level at the output terminal while the p-channel transistor is cutoff.
In certain applications, the voltage swing provided at an output terminal may be greater than the voltage swing required to drive external circuitry coupled to the output terminal. More particularly, for example, a typical external voltage supply in CMOS circuits is 5 volts, and a typical voltage swing at the output terminal is approximately 5 volts, between 0 volts and 5 volts. In TTL logic, however, a typical voltage swing is approximately 3.3 volts, between 0 volts and 3.3 volts. Consequently, it often is not necessary to use the typical full CMOS voltage swing to drive circuitry from another logic family such as the TTL family.
Generally, more time is required to achieve a full voltage swing than is required to achieve less than a full voltage swing. Thus, transitions of an output signal between high and low voltage states can be slowed by undertaking a full logic swing when less than a full logic swing will suffice.
One way to reduce the voltage swing where less than a full swing is required to drive the external circuitry is to couple the p-channel pull-up transistor to a lower level voltage supply so that the p-channel device pulls the output terminal up to a voltage level which is less than the voltage level provided by a typical external power supply. For example, for a CMOS output buffer circuit driving a typical TTL load, a lower level power supply of approximately 3.3 volts ordinarily would be sufficient.
One possible approach to implementing such a lower level power supply is to provide it externally. Unfortunately, the use of an extra external power supply can be unduly burdensome.
Another possible approach to implementing such a lower level power supply is to integrate it into the same chip as the output buffer. This can be a problematic solution as well. More specifically, for example, an output buffer circuit may be called upon to drive a relatively large capacitive load. Unfortunately, it can be quite difficult to construct an on-chip lower level voltage supply that has a sufficiently low output impedance to drive such a large capacitive load.
Therefore, there has been a need for a CMOS output buffer circuit in which the voltage swing at the output terminal can be less than the full voltage swing permitted by typical external voltage supplies. Moreover, there has been a need for such an output buffer circuit which can be economically constructed and which is capable of driving relatively large capacitive loads. The present invention meets these needs.